Alif Semiconductor /AE302F80F5582LE_CM55_HE_View /LPPDM /PDM_CTL0

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Interpret as PDM_CTL0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Val_0x0)CH0_EN 0 (Val_0x0)CH1_EN 0 (Val_0x0)CH2_EN 0 (Val_0x0)CH3_EN 0 (Val_0x0)CH4_EN 0 (Val_0x0)CH5_EN 0 (Val_0x0)CH6_EN 0 (Val_0x0)CH7_EN 0 (Val_0x0)PDM_MODE 0 (FIFO_CLR)FIFO_CLR

CH6_EN=Val_0x0, CH2_EN=Val_0x0, PDM_MODE=Val_0x0, CH5_EN=Val_0x0, CH1_EN=Val_0x0, CH0_EN=Val_0x0, CH7_EN=Val_0x0, CH3_EN=Val_0x0, CH4_EN=Val_0x0

Description

PDM Audio Control Register 0

Fields

CH0_EN

Channel 0 enable.

0 (Val_0x0): Disable and soft-clear

1 (Val_0x1): Enable

CH1_EN

Channel 1 enable.

0 (Val_0x0): Disable and soft-clear

1 (Val_0x1): Enable

CH2_EN

Channel 2 enable.

0 (Val_0x0): Disable and soft-clear

1 (Val_0x1): Enable

CH3_EN

Channel 3 enable.

0 (Val_0x0): Disable and soft-clear

1 (Val_0x1): Enable

CH4_EN

Channel 4 enable.

0 (Val_0x0): Disable and soft-clear

1 (Val_0x1): Enable

CH5_EN

Channel 5 enable.

0 (Val_0x0): Disable and soft-clear

1 (Val_0x1): Enable

CH6_EN

Channel 6 enable.

0 (Val_0x0): Disable and soft-clear

1 (Val_0x1): Enable

CH7_EN

Channel 7 enable.

0 (Val_0x0): Disable and soft-clear

1 (Val_0x1): Enable

PDM_MODE

PDM clock frequency selection for all channels. For more details about these modes,PDM Modes.

0 (Val_0x0): PDM mode 0

1 (Val_0x1): PDM mode 1

9 (Val_0x9): PDM mode 9

FIFO_CLR

FIFO clear

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